This invention is in the field of solid-state memories. Embodiments of this invention are more specifically directed to the sensing of stored data states in such memories.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. The computational power of these modern devices and systems is typically provided by one or more processor “cores”. These processor cores operate as a digital computer, in general retrieving executable instructions from memory, performing arithmetic and logical operations on digital data retrieved from memory, and storing the results of those operations in memory. Other input and output functions for acquiring and outputting the data processed by the processor cores are performed as appropriate. Considering the large amount of digital data often involved in performing the complex functions of these modern devices, significant solid-state memory capacity is now commonly implemented in the electronic circuitry for these systems.
Static random access memory (SRAM) has become the memory technology of choice for much of the solid-state data storage requirements in these modern power-conscious electronic systems. As is fundamental in the art, SRAM cells store contents “statically”, in that the stored data state remains latched in each cell so long as power is applied to the memory; this is in contrast to “dynamic” RAM (“DRAM”), in which the data must be periodically refreshed in order to be retained.
FIG. 1a illustrates an example of a conventional SRAM cell 2, which is constructed in the well-known six-transistor (6-T) arrangement. In this example, cell 2 is in the jth row and kth column of a memory array of similar cells, and is biased between the voltage on power supply line Vdda and a ground reference voltage Vssa. SRAM memory cell 2 is constructed in the conventional manner as a pair of cross-coupled CMOS inverters, one inverter of series-connected p-channel load transistor 3a and n-channel driver transistor 4a, and the other inverter of series-connected p-channel load transistor 3b and n-channel transistor 4b; in the usual manner, the gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter. The common drain node of transistors 3a, 4a constitutes storage node SNT, and the common drain node of transistors 3b, 4b constitutes storage node SNB, in this example. N-channel pass transistor 5a has its source/drain path connected between storage node SNT and bit line BLTk for the kth column, and n-channel pass transistor 5b has its source/drain path connected between storage node SNB and bit line BLBk. The gates of pass transistors 5a, 5b are driven by word line WLj for this jth row in which cell 2 resides.
Bit lines BLTk, BLBk are shared by other cells 2 in the same column k, and are connected (typically via transfer gates, and perhaps also by way of column select circuitry, neither shown in FIG. 1a) to sense amplifier 12. Sense amplifier 12 is constructed similarly as cell 2, in that it includes a pair of cross-coupled inverters: one inverter being series-connected p-channel load transistor 13a and n-channel driver transistor 14a, and the other inverter of series-connected p-channel load transistor 13b and n-channel transistor 14b. The gates of the transistors in each inverter are connected together and to the common drain node of the transistors in the other inverter, in the usual manner. In sense amplifier 12, the common drain node of transistors 13a, 14a constitutes sense node ST, which is coupled to bit line BLTk, while the common drain node of transistors 13b, 14b constitutes storage node SB, coupled to bit line BLBk. In contrast to cell 2, however, ground bias is applied to sense amplifier 12 via n-channel MOS enable transistor 15, which has its drain connected to the source nodes of transistors 14a, 14b, and its source at ground voltage Vss. The gate of enable transistor 15 receives sense amplifier enable signal SAE.
In its normal operation, bit lines BLTk, BLBk are typically precharged by precharge circuitry 7 to a high voltage Vddp (which is at or near power supply voltage Vdda) and are equalized to that voltage; precharge circuitry 7 then releases bit lines BLTk, BLBk to then float during the remainder of the access cycle. During this time, sense amplifier enable signal SAE is inactive low, turning off enable transistor 15, which disables the operation of sense amplifier 12. To access cell 2 for a read operation, word line WLj is then energized, turning on pass transistors 5a, 5b, and connecting storage nodes SNT, SNB to bit lines BLTk, BLBk. Upon sense amplifier enable signal SAE being driven active high, the differential voltage developed on bit lines BLTk, BLBk by selected cell 2 is sensed and amplified by the cross-coupled inverters of sense amplifier 12. To write data, typical SRAM memories also include write circuitry that pulls one of bit lines BLTk, BLBk low (i.e., to a voltage at or near ground voltage Vssa), depending on the data state to be written. Upon word line WLj then being energized, the low level bit line BLTk or BLBk will pull down its associated storage node SNT, SNB, causing the cross-coupled inverters of addressed cell 2 to latch in the desired state.
In any type of solid-state semiconductor memory, the sensing of data stored in a selected memory cell is a critical operation. Accurate sensing of the stored memory cell state must be maintained over varying voltage and temperature conditions, variations in manufacturing parameters, and in the presence of system noise. As a result, the precision of the sense circuitry plays a role in determining the memory density in bits per unit “chip” area (and thus in the cost-per-bit of manufacturing the memory), because the noise margin of the sense circuitry determines, in large part, the minimum memory cell size required to provide the necessary read current. The timing of the sense operation in an SRAM constructed as shown in FIG. 1a has become especially critical as transistor feature sizes have continued to shrink.
FIG. 1b is a timing diagram illustrating an example the timing of sense amplifier enable signal SAE relative to the access of a conventional SRAM cell 2. In this example, SRAM cell 2 of FIG. 1a is storing a “0” data state (i.e., storage node SNT is at a low “0” level, and storage node SNB is at a high “1” logic level), and is being read during a read cycle in which its row j is selected. At the beginning of the cycle shown in FIG. 1b, for example at time t0, bit lines BLTk, BLBk are both precharged to a high logic level by bit line precharge circuitry 7. Word line WLj is at a low logic level, maintaining pass transistors 5a, 5b off In SRAM cell 50jk in this example, storage nodes SNT, SNB will be at full “0” and “1” logic levels, respectively, corresponding to the stored “0” data state. Because pass transistors 5a, 5b are both off with word line WLj low, the precharged levels at bit lines BLTk, BLBk are isolated from storage nodes SNT, SNB. Sense amplifier enable signal SAE is at an inactive low level at this time, disabling the operation of sense amplifier 12.
In this example, word line WLj is energized to a high logic level at time t1, to select row j including cell 2. Pass transistors 5a, 5b couple storage nodes SNT, SNB to their respective bit lines BLTk, BLBk. Cell 2 is storing a “0” data state in this example, and as such, upon word line WLj being energized and pass transistor 5a being turned on, the voltage at bit line BLTk will be affected by the low level at storage node SNT. For this data state, in which high logic level is driven at storage node SNB, bit line BLTk begins to be discharged by driver transistor 4a of cell 2 when pass transistor 5a is turned on by word line WLj after time t1. Because driver transistor 4b will be off for this data state, bit line BLBk will not be significantly discharged from its precharged high level.
Three possible timings of sense amplifier enable signal SAE are shown in FIG. 1b, by way of example. At time tearly, the differential voltage ΔV1 at bit lines BLTk, BLBk is quite small, as compared with the differential voltages ΔV2, ΔV3 at later times tx and tlate respectively. If sense amplifier enable signal SAE is driven high at time tearly, the sensing operation by sense amplifier 12 is vulnerable to error caused by noise of a magnitude greater than the small bit line differential voltage ΔV1 at that time. On the other hand, the driving of sense amplifier enable signal SAE high at time tlate may be later than necessary for reliable sensing over the voltage and temperature range of the memory. For example, if differential bit line voltage ΔV2 provides sufficient noise margin to the sensing operation, the larger differential bit line voltage ΔV3 may not provide any practical benefit. In this case, the later sense time tlate would unduly lengthen the read access time by the delay of time tlate from the optimal time tx.
It has been observed that the design of modern SRAM circuitry to optimally time the driving of the sense amplifier control signal can be quite difficult. Various conventional techniques for interlocking the sense control signal in SRAM devices have been developed.
FIG. 1c illustrates one conventional approach for determining sense amplifier timing. In this example of memory array 20, one row is selected by one of row drivers 17, corresponding to the row address decoded by row decoder 16, driving an active level on a word line WL. As described above, each sense amplifier 12 is enabled by a corresponding enable transistor 15 that receives sense amplifier enable signal SAE at its gate. In this example, sense amplifier enable signal SAE is driven by inverter chain 19, which receives a row enable control signal ROW_EN that gates each of row drivers 17. In operation, in response to a low-to-high transition of row enable control signal ROW_EN, the row driver 17 addressed by row decoder 16 will drive its associated word line WL to an active high level, turning on the pass transistors in each cell in that row. The low-to-high transition of row enable signal ROW_EN is also received by inverter chain 19, which in turn, after the propagation delay through the inverters in inverter chain 19, initiates sense amplifier enable signal SAE that is applied to the gates of enable transistors 15.
While the conventional solution shown in FIG. 1c can be designed to nominally generate sense amplifier enable signal SAE at a desired time, this approach is subject to certain limitations. A first such limitation stems from the difference in construction between the memory cell transistors (i.e., load transistors 3a, 3b; driver transistors 4a, 4b; pass transistors 5a, 5b) in array 20 and the “logic” transistors that make up inverter chain 19 outside of array 20. In modern integrated circuits, in which significant differences in channel lengths, threshold voltages, and the like are incorporated into the ultimate structure, the electrical characteristics of the logic transistors will differ from those of the cell transistors that the logic transistor behavior will not closely match that of the array transistors. In integrated circuits realized at modern sub-micron feature sizes, the smaller cell transistors are generally not permitted outside of the array boundaries due to their significant differences in design rules and manufacturability, which prohibits the fabrication of inverter chain 19 using cell transistors; in addition, it has been observed that localized variation in device behavior of the small geometry cell transistors can be significant, which reduces the benefit of realizing inverter chain 19 using cell transistors outside of the array even if it were permitted. This mismatch is exacerbated in state of the art technologies, in which the cell transistors within array 20 and logic transistors outside of array 20 are fabricated largely with independent processes, such as different pocket or Vt-adjust ion implants, different gate dielectric processing (e.g., fluorinated gate oxide in the cell transistors), and the application of transistor length biasing to one transistor type but not the other. These processing differences reduce the correlation of logic transistors to cell transistors even further, worsening the ability of inverter chain 19 to adjust sense amplifier timing in response to process variations. As such, designs that rely on an inverter chain or other logic transistor delay stages external to the memory for sense amplifier timing will necessarily include some additional design margin (i.e., additional delay in generating sense amplifier enable signal SAE), which adversely impacts read access times.
FIG. 1d illustrates another conventional approach to determining sense amplifier timing. In this example, rather than inverter chain 19 of FIG. 1c, replica row drivers 22 receive the row enable control signal ROW_EN, and drive reference word lines RWL applied to replica mini-array 24 accordingly. Replica mini-array 24 is a small array of “dummy” memory cells, constructed using the same transistor sizes as in main array 20, but located outside of array 20. One or more of those “dummy” memory cells have hard-wired data states that are reflected on reference bit lines RBL. Reference bit lines RBL are connected to inputs of sense driver 25, which drives sense amplifier enable signal SAE upon receiving the communicated data state of the “addressed” dummy memory cells. Typically, multiple dummy cells along one or more columns of replica mini-array 24 are ganged together to minimize the effects of local device variation.
In operation, reference word lines RWL are driven high by replica row drivers 22 in response to a transition of row enable control signal ROW_EN. Upon reference word lines RWL charging to a sufficient voltage to turn on pass transistors in the associated dummy memory cells, and upon the accessed dummy memory cells discharging reference bit lines RBL to a low level, sense driver 25 then asserts sense amplifier enable signal SAE. This conventional approach improves on the inverter chain delay stage of FIG. 1c, by theoretically constructing the delay elements similarly as the cell transistors in main array 20, thus providing a proxy for the effects of the parasitic impedance of reference word lines WL, bit line transistors, and cell transistors. However, the chip area required to implement replica mini-array 24 can be significant, especially in those technologies requiring dummy cells at the edge of the replica memory cells in order to absorb proximity effects, or to implement terminations and “keepouts”. And while replica mini-array 24 will mimic the parasitic resistance and capacitance of the word lines and bit lines of main array 20, it is still only a proxy for those effects, and will not necessarily match all process, voltage, and temperature variations. Furthermore, this construction will not track on-chip variations in read current among the cells of main array 20. Accordingly, the approach of FIG. 1d is contemplated to be an expensive (in chip area) technique for generating sense amplifier enable signal SAE, while still not closely matching or tracking the actual optimum timing.
Arslan et al., “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Custom Integrated Circuits Conference (IEEE, 2008), pp. 415-418, describes the incorporation of a replica column of memory cells implemented in or adjacent to the main memory array, in which the discharge of the replica bit line by a configurable number of dummy memory cells in that column drives the sense amplifier enable signal. Amrutur et al., “A Replica Technique for Wordline and Sense Control in Low-Power SRAM's”, J. Solid State Circuits, Vol. 33, No. 8 (IEEE, 1998), pp. 1208-19, describes a row of replica cells implemented in or adjacent to the main memory array, for which a dummy global word line is driven along with the global word line for the main array. The discharge of replica bit lines by replica memory cells selected by the dummy global word line drives the sense amplifier enable signal.